The design proposed here concerns bidirectional linear Very Large Scale Integration (VLSI) processor arrays. No technique has yet been developed to enable such a design where the data items enter the array in consecutive time moments. The problem to be resolved was how to organize the array and the cells to enable each data item to meet all the elements from the other data stream.

The developed design shows that such an array exists and only the processor cell is slightly more complex. All other VLSI constraints for local communication and regular data flow are fulfilled.

This design shows a speedup of 2 according to the standard bidirectional linear array and a 50% reduction in the number of processors used. This results in a fourfold increase in efficiency, which means that finally the limit of 100% efficiency can be reached by the bidirectional linear arrays.