It has become an irreversible trend in recent years that the semiconductor wafer fabrication requires shorter processing time, greater flexibility and lower capital cost. Rapid thermal processing (RTP) has demonstrated its potential to meet such requirements while becoming a key process for manufacturing advanced semiconductor devices. Ever decreasing feature sizes require extremely tightly controlled processing conditions, especially the temperature trajectory to be precisely followed across the wafer. This paper presents a systematic methodology for RTP chamber design, based on the 3-dimensional physics-based model of a generic RTP chamber. After experimentally validated, the physics-based model is reduced to a lower-order model without sacrificing its fidelity for computational efficiency. With a reduced-order model, optimization studies are performed to determine how small the deviation of the wafer temperature from the pre-specified trajectory can be made in a given design. The results of the optimization studies indicate the goodness of the given RTP design, unravel clues for design improvements, and may provide guidelines for control implementation.