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AN EFFICIENT NETWORK ANALYSER BASED ON LINEAR ARRAY ARCHITECTURE 1  

Authors: S. N. Metallinos a;  D. I. Reisis ab; G. I. Stassinopoulos a
Affiliations:   a Division of Computer Science, Department of Electrical Engineering, National Technical University of Athens, Athens, Greece
b Division of Applied Physics, University of Athens,
DOI: 10.1080/10637199408915412
Publication Frequency: 6 issues per year
Published in: journal International Journal of Parallel, Emergent and Distributed Systems, Volume 2, Issue 1 & 2 1994 , pages 139 - 147
Formats available: PDF (English)
Previously published as: Parallel Algorithms and Applications (1063-7192) until 2005
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Abstract

In this paper we present an array based network analyzer for Broadband Integrated Services Digital Networks. The analyzer is laid as a linear array processor. We describe the implementation of the analyzer's functions on the array processor. Apart the real-time application, the importance of this study becomes more apparent by the fact that, the resulting design can be implemented on configurable gate array and be attached to a microprocessor. Nevertheless, it is also possible to use the analyser array in combination with commercially available hardware to debug the network equipment in the development phase.
1 This work has been supported in part by EEC project RACE R1083.
Keywords: Linear arrays; string matching; broadband networks; network analyzer
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