A satisfiability formulation for FPGA routing with pin rearrangements

Authors: F. He ^a; W. N. N. Hung ^b; X. Song ^c; M. Gu ^a; J. Sun ^a

Affiliations:	^a School of Software, Tsinghua University, Beijing, China
	^b Synplicity Inc., California, USA
	^c Department of Electrical and Computer Engineering, Portland State University, Oregon, USA

DOI: 10.1080/00207210701650661

Publication Frequency: 12 issues per year

Published in: journal

International Journal of Electronics, Volume 94, Issue 9 September 2007 , pages 857 - 868

Subjects: Circuits & Devices; Communication Networks & Systems; Communications & Information Processing; Digital Signal Processing; Electrical Engineering Communications; Electromagnetics & Microwaves; Instrumentation, Measurement & Testing; Nanoscience & Nanotechnology; Optics, Optoelectronic Effects, Devices & Systems; Semiconductors; Systems & Control Engineering; Telecommunications;

Formats available: HTML (English) : PDF (English)

Previously published as: Journal of Electronics and Control (0368-1947) until 1965

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